Solid phase crystallization (SPC) and solid phase epitaxy (SPE) are conventionally used to form Si, SiGe, and Ge films for solid state electronics. However, controlling grain growth can be a problem for process integration because grain boundaries may occur in unwanted locations, which limit device performance and reliability.
In SPC, a film of homogeneous amorphous material is formed having a uniform crystallization temperature (Tc). Upon heating to a temperature above the Tc, nucleation occurs at random locations throughout the film, and the material crystallizes starting at the nucleation sites. Eventually, grain boundaries form at interfaces where different crystalline structures meet. These grain boundaries may occur randomly throughout the film.
In SPE, a film stack is formed having sections of material having varying crystallization temperatures. As the stack is heated above the Tc of one section, crystallization begins. The material with a lower Tc can “seed” crystallization of the material with the higher Tc. The benefit of this method is that crystallization can be performed at a relatively lower temperature. However, this method may also cause the formation of grain boundaries at undesired locations. For example, if a lower-Tc material is above and below a higher-Tc material, a grain boundary typically forms within the higher-Tc material as the higher-Tc material crystallizes from both sides. The grain boundary is generally nonplanar due to random orientation of grains within the different lower-Tc materials. Such grain boundaries may limit the use of these materials in certain applications, such as vertical thin-film transistors (TFTs).